ATM is a transfer mode in which information is organized into cells. It is asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. ATM is a layered architecture allowing multiple services like voice, data and video to be mixed over the network.
It is desirable that a common interface between the lowest physical layer (PHY) and upper layer modules such as the ATM layer is defined, to thereby allow a common PHY interface in ATM subsystems across a wide range of speeds and media types.
In many cases, an arrangement is provided, where a plurality of PHY devices are connected via the PHY interface to a single ATM device. Thus, an address has to be allocated to the PHY devices, which is used by the higher layer device in order to individually access one of the PHY devices in order to perform a data transfer. However, the number of available addresses according to the PHY interface specification may not be large enough to support a desired number of physical devices.
Although conversion circuits such as multiplexer/demultiplexer (MUX/DEMUX) circuits are known to connect a plurality of non-addressable PHY devices to a higher layer device, these circuits are not suitable for overcoming the above problem, because they also demand a respective address for each of the non-addressable PHY devices.